CMOS technology has been scaling down in size for 40 years under the guidance of Moore's law. To continue scaling, tunnel field-effect transistors (TFETs) such as finFETs, are being used. It has been understood that TFETs have advantages for low-power applications because of its' intrinsic low sub-threshold swing and low off-state leakage. TFETS are further improved by using strained silicon. Strained silicon refers to the application of stress (uniaxial and biaxial stress) in the structure to create changes in the direct gate tunneling current. Decreases/increases in the gate tunneling current for various stresses primarily result from repopulation into a sub-band with a larger/smaller out-of-plane effective mass. Hole tunneling current is found to decrease for biaxial and uniaxial compressive stress and increase for biaxial tensile stress. For p-type finFETs, the gate tunneling current increases for biaxial tensile stress but decreases for biaxial and longitudinal compressive stresses. For n-type finFETS, the opposite occurs. FinFET devices are being adopted for advanced CMOS technology nodes such as 22 nm, 14/16 nm, and future 10 nm and 7 nm node, for improved drivability and short channel effect. However, traditional strain enhancement such as embedded SiGe (for p-channel metal-oxide-semiconductor—“PMOS”) has shown reduced effectiveness due to smaller SiGe volume from scaled fin source and drain regions.
Accordingly, there is a need for systems, apparatus, and methods that improve upon conventional strain enhancement approaches including the improved methods, system and apparatus provided hereby. The inventive features that are characteristic of the teachings, together with further features and advantages, are better understood from the detailed description and the accompanying figures. Each of the figures is provided for the purpose of illustration and description only, and does not limit the present teachings.